(a) Field of the Invention
The present invention relates to a method for high-speed programming of a nonvolatile semiconductor memory device and, more particularly, to a technique for programming of an EEPROM or flash EEPROM having a multi-valued memory cell.
(b) Description of the Related Art
EEPROM (Electrically Erasable and Programmable Read Only Memory) and flash EEPROM are known in the art as non volatile memory devices wherein the memory cells are electrically programmed and erased.
FIG. 1 shows the structure of a typical memory cell of a known flash EEPROM, wherein n-conductivity type source 102 and drain 101 are formed on the surface of a p-conductivity type silicon substrate 100, with a channel region 103 disposed therebetween. A tunnel oxide film 104, a floating gate 105, an interlevel dielectric film 106 and a control gate 107 are consecutively formed above the channel region 103. The source 102 and the drain 101 are connected to a source line 109 and a bit line 108, respectively.
Programming of the memory cell in the flash EEPROM is effected, for example, by applying about 12 volts to the control gate 107, about 5 volts to the drain 101 and zero volts to the source 102, with the substrate 100 maintained at a ground potential, so as to raise the potential of the floating gate 105 by using capacitive coupling between the control gate 107 and the floating gate 105. The potential rise of the floating gate 107 forms a channel between the source 102 and the drain 101, and the voltage between the control gate 107 and the drain 101 generates hot electrons in the vicinity of the drain 101, which are injected into the floating gate 105 against the potential barrier (3.2 electron volts for electrons, for example) between the silicon substrate 100 and the tunnel oxide film 104.
The injected electrons stay in the floating gate 105 after programming, to thereby raise the threshold of the MOSFET or memory cell, because the floating gate 105 is surrounded by the insulator film.
The erasing operation is effected by applying about 12 volts to the source 102, with the control gate 107 grounded, so as to pull out the electrons from the floating gate 105, thereby lowering the threshold voltage of the MOSFET. In this example, the memory cell has a binary threshold voltage.
It is proposed recently that the EEPROM have more than binary data or multi-valued data in each memory cell, namely, a single memory cell have multi-valued states for the threshold.
Referring to FIG. 2 showing a schematic configuration of a nonvolatile semiconductor memory device having multi-valued data, a row decoder 203, which receives an output from a variable voltage generator 204, supplies an active signal to one of a plurality of word lines each connected to the control gates of a row of memory cells in a memory cell array. A row of the memory cell array includes a plurality of groups or pages of memory cells each disposed in a plurality of (8 in this example) columns 223 to 230 to be programmed at a time in a parallel programming operation.
The drains of the memory cell in each column is connected to a bit line connected to a corresponding one of write blocks 207 to 214 through a corresponding one of column decoders 215 to 222. The write blocks 207 to 214 are supplied with programming pulses from a column pulse generator 201 for parallel programming. The input address data in the input data 206 are supplied to the row decoder 203 and the column decoders 215 to 222, which select one of word lines and one of bit lines, respectively, to select a corresponding memory cell.
A program data sense block 205 receives input data 206 to sense the number of data values in a parallel programming step for a page of memory cells. The program data sense block 205 controls the variable voltage generator 204 and the column pulse generator 201 to provide a programming voltage to a selected word line and provide constant voltage pulses ranging from zero to several pulses in number to selected bit lines for the page, respectively.
A technique for programming of multi-valued data to a memory cell is described in, for example, Patent Publication JP-A-6-267285, which may be applied to a parallel programming mode. Referring to FIG. 3, the technique includes application of a sequence of programming voltages, or a stepwise-rising voltage pulse rising from zero volt to 12 volts through 10 volts and 11 volts and staying at the respective voltage levels for 1 millisecond (ms) each, to the control gates of a selected row of the memory cells through a selected word line and application of a 8.5-volt pulse to a bit line for 0.8 ms from the column pulse generator at the timing of the desired voltage level of the stepwise rising voltage, thereby injecting hot electrons in a corresponding amount to the floating gate of the specified memory cell for programming. After the programming, the specified memory cell has a threshold voltage based on one of the voltage levels of the stepwise-rising voltage, which correspond to "00", "01", "10" and "11" of the data for the multi-valued memory cell, wherein either data "00" or "11" corresponds to a state of the memory cell which is not programmed or erased.
Referring to FIG. 4 showing variation of the threshold voltage after the programming operation by the programming voltage shown in FIG. 3, the number of memory cells (or number of bits) is plotted on abscissa against threshold voltage of the memory cells plotted on ordinate. Assuming that data "11" corresponds to an erased state, for example, the arrow designated by 301 illustrates the threshold rise of the memory cell programmed by 10 volts, or first programming voltage. Similarly, arrows 302 and 303 correspond to the threshold rise of the memory cells programmed by 11 volts (second programming voltage) and 12 volts (third programming voltage), respectively, to obtain data "01" and "00".
A verifying operation is generally conducted to the multi-valued memory cell after the programming thereof, wherein it is examined whether the memory cell has a desired threshold voltage corresponding to the programming voltage applied. The verifying operation is effected by comparing the threshold voltage of each memory cell against the reference voltage level ref.1 (7 volts), ref.2 (5.5 volts) or ref.3 (4 volts) by applying a read voltage to the selected bit line and word line to thereby judge the threshold voltage level. If the memory cell does not have a desired threshold range, then the application of the programming voltage and a verifying operation are repeated until the memory cell exhibits a desired threshold range.
More specifically, for example, if the value of a programming data is "10", the threshold voltage of the programmed memory cell is compared against 4 volts. If it is judged that the threshold voltage is higher than 4 volts, the threshold voltage is then compared against 5.5 volts. If it is judged that the threshold voltage is below 5.5 volts, then the threshold voltage is judged to be correct, thereby completing the programming operation of the memory cell. Otherwise, if it is judged that the threshold voltage is below 4 volts, the programming and verifying operation is repeated. Similarly, if the value of the programming data is "01" or "00", the threshold voltage is examined whether it resides between 5.5 volts and 7 volts or above 7 volts.
In the conventional method for programming multi-valued memory cells in the flash EEPROM, the programming time length is generally large, and accordingly, a higher programming voltage may be desired together with a plurality of programming steps irrespective of value for the parallel programming data so as to reduce the time length for the single programming operation, although the higher programming voltage increases the number of programming steps and verifying steps.
Referring to FIG. 5, there are shown relationships between the threshold voltage and the time length for programming by the respective data by applying the corresponding programming voltages, wherein each data can be obtained after 50 microseconds (.mu.s) of programming. The graph also shows the threshold voltage after the programming by the third programming voltage of 12 volts, which corresponds to data "00". The threshold voltage reaches to the first level corresponding to data "10" after 1 .mu.s, to the second level corresponding to data "01" after 10 .mu.s, and to the third level corresponding to data "00" after 50 .mu.s. In this respect, data "01" and "10" can be obtained in a higher rate by the application of the higher programming voltage.
Referring to FIG. 6 showing variation of the threshold voltage in three samples of memory cells during programming to data "00" and data "10" by applying the respective programming voltages, it can be seen that data "00" corresponding to the higher programming voltage generates a large variation in the threshold voltages during the programming step. This results in a large variation in the threshold voltage for data "10" or "01" after the programming by the higher voltage level.
As a result of the variation after applying the higher programming voltage to the memory cell irrespective of the values for the programming data, the graph of variation in the threshold voltage shown in FIG. 4 changes to the graph shown in FIG. 7. Specifically, the higher programming voltage, which increases the variation in the threshold voltage, generates a significant number of error bits having threshold voltages exceeding the boundary threshold voltages ref.3, ref.2 and ref.1. In order to avoid the occurrence of the error bits, the repeated number of programming and verifying steps in a single programming operation should be increased, which increases the programming time length however.
In FIG. 5, if a plurality of combinations of a programming and verifying step are to be effected in a single programming operation by using the higher programming voltage, wherein it is assumed that a programming step and a verifying step consumes 200 nanoseconds (ns) and 1 .mu.s, respectively, a complete programming operation for data "00" requesting 50 .mu.s of application of the higher programming voltage must be effected for as large as 250 times (50 .mu.s/250 ns=250), which consumes a large programming time. This example will be mentioned later as a second convential technique.